The whole machine — and which parts each instruction lights up

Pick an instruction below. The parts it uses light up; the parts it ignores go faint. The control signals update underneath. This is the picture the exam asks you to draw.

How the instruction bits are routed

Bits	Go to
Instruction [6-0]	Control unit (the opcode)
Instruction [19-15]	Read register 1 (rs1)
Instruction [24-20]	Read register 2 (rs2)
Instruction [11-7]	Write register (rd)
Instruction [31-0]	Imm Gen (the whole word)
Instruction [30, 14-12]	ALU control (funct7 bit 30 + funct3)

The one Boolean equation you must know

PCSrc = Branch AND Zero

PCSrc is not a direct output of the Control unit. The Control unit produces Branch; the ALU produces Zero; an AND gate combines them. So a beq only takes the branch when both are 1.

Kid version: "Am I a branch instruction?" AND "were the two numbers equal?" Both yes → jump. Otherwise carry on to PC+4.

Path walk-through: R-type (e.g. add x1, x2, x3)

PC → instruction memory, fetch. PC+4 computed and selected (PCSrc = 0).
Bits [19-15] and [24-20] read two registers.
Read data 1 → ALU input A. Read data 2 → ALUSrc mux input 0 → ALU input B (ALUSrc = 0).
ALU does what ALU control says (ALUOp = 10 → funct decides).
ALU result → MemtoReg mux input 0 (MemtoReg = 0) → back along the bottom to Write data.
Bits [11-7] pick the write register; RegWrite = 1 commits it.

Data memory is bypassed entirely, and Branch = 0.

Path walk-through: load (ld x1, offset(x2))

Fetch, PC+4 as usual.
Bits [19-15] read the base register → ALU input A.
Imm Gen sign-extends the offset → ALUSrc mux input 1 → ALU input B (ALUSrc = 1).
ALU adds (ALUOp = 00) → the memory address → Data memory Address.
MemRead = 1 → Read data comes out.
Read data → MemtoReg mux input 1 (MemtoReg = 1) → Write data. RegWrite = 1.

Read register 2 and the Data memory Write data input are unused.

Path walk-through: store (sd x1, offset(x2))

Same address calculation as a load (ALUSrc = 1, ALU adds). But now Read data 2 goes to Data memory Write data, MemWrite = 1, and RegWrite = 0 — nothing is written back to the register file, so MemtoReg is a don't-care.

Path walk-through: beq x1, x2, offset

Fetch. PC+4 goes to PCSrc mux input 0.
PC also goes to the branch adder.
Imm Gen → Shift left 1 → branch adder's other input.
Branch adder → Sum = branch target → PCSrc mux input 1.
Both registers read → ALU with ALUSrc = 0; ALUOp = 01 → ALU control 0110 → subtract.
Zero AND Branch → PCSrc. Equal → take the branch; not equal → PC+4.

No register write, no memory access.

The critical path

The load instruction is the critical path: Instruction memory → register file → ALU → data memory → register file. It is the longest route, so it sets the clock period for the whole single-cycle machine. Every other instruction finishes early and then waits — which is why single-cycle "violates the design principle of making the common case fast".